1. Field of the Invention
This invention relates generally to semiconductor processing, and more specifically to multi-level interconnects with low dielectric constant insulators and methods for fabricating the same.
2. Background Art
Modern integrated circuits are made up of literally millions of active and passive devices such as transistors, capacitors, and resistors. These devices are initially isolated from one another but are later connected together to form functional circuits through interconnect structures. The quality of the interconnect structure drastically affects the performance and reliability of the fabricated circuit. Interconnects are increasingly determining the limits of performance and density of modern ultra large scale integrated (ULSI) circuits.
Conventional interconnect structures employ one or more metal layers. Each metal layer is typically made from aluminum alloys or tungsten. Interlevel and intralevel dielectrics (ILDs), such as silicon dioxide (SiO.sub.2), are used to electrically isolate active elements and different interconnect signal paths from each other. The electrical connections between different interconnect levels are made through vias that are formed in the ILD layers. Typically, the vias are filled with a metal, such as tungsten.
Recently, there has been great interest to replace SiO.sub.2 with low-dielectric-constant ("low-k") materials as the ILD in interconnect structures. It is desirable to employ low-k materials as insulators in IC interconnect because these low-k materials reduce the interconnect capacitance. Accordingly, these low-k materials increase the signal propagation speed while reducing cross-talk noise and power dissipation in the interconnect.
However, the use of low-k materials as ILD in the interconnect is not mature at this time, and processes still need to be developed for accommodating the low-k material when forming the interconnect. When forming ILDs entirely out of low-k materials, almost all interconnect processing steps need to be developed, such as the following steps: chemical mechanical polishing (CMP) of the low-k materials, via etch into the low-k ILD layer, post via etch clean, and metal via fill into the low-k ILD layer.
Attempts have been made to provide a process for an embedded low-k dielectric integration approach that employs the low-k dielectric for filling only the gaps between metal lines in the interconnect structure, while still employing conventional SiO.sub.2 in the rest of the ILD. U.S. Pat. No. 5,486,493 to Jeng, entitled "Planarized Multi-level Interconnect Scheme With Embedded Low-Dielectric Constant Insulators," describes one such approach to embed low-k dielectric in the interconnect structure.
The advantage of this approach is that, since the low-k film is only used to fill the gaps between the metal lines, many of the above-mentioned interconnect processing steps are the steps utilized for conventional SiO.sub.2 ILD. This approach attempts to avoid the difficulties associated with (1) having to etch a via through a low-k film; (2) having to make the post-via-etch clean for the low-k film, and (3) having to fill metal through the low-k film for the via plugs.
Unfortunately, these embedded low-k dielectric integration processes suffer from the following disadvantages. For example, ensuring that the level of the low-k material is the same as the top surfaces of the metal or interconnect lines is difficult for at least four reasons. First, in practical manufacturing, it is impossible to deposit a film of low-k material at a precise film thickness from wafer to wafer. Second, even within a wafer, depositing an absolutely uniform low-k film across the same wafer is not possible, since the typical thickness non-uniformity of the low-k film deposited by either spin-on coating or chemical vapor deposition (CVD) using currently-available technology varies by about one to ten percent. Third, even within a given die on a wafer, the gaps between the metal lines are of different sizes, leading to uneven film height of the low-k material above the metal lines. The larger gaps or spacings are filled with more low-k material, thereby lowering the height of the low-k material in these areas. In contrast, the smaller gaps or spacing are filled with less low-k material, thereby raising the height of the low-k material in these areas. Fourth, removing low-k film to the precise thickness during the etch-back is impossible to control in manufacturing.
This difficulty of controlling the deposition and etch-back of the low-k material so that the surface level of the low-k material is the same as the top surfaces of all the metal or interconnect lines results in the following two problems: (1) insufficient-etch-back of the low-k material, which results in a poisoned via and problems associated therewith, and (2) excessive-etch-back of the low-k material, which results in the increase in inter-metal line capacitance and problems associated therewith.
Consequently, applying the correct etch-back amount for the low-k material with the required tolerance (hereinafter referred to as a "process window") is difficult for these proposed processes that embed low-k materials. This problem can be characterized as: "the low-k material etch-back has a very narrow process window." Missing the process window, for whatever reason, results in poor interconnect integrity and reliability, or degradation in interconnect performance.
A conventional method for embedding a low dielectric constant (low-k) material in an interconnect structure involves the following process steps. A first metal layer is deposited on a substrate 1 and patterned to form metal lines 2. Thereafter, a low-k dielectric material 3 is deposited over substrate 1 and metal lines 2. FIG. 1A illustrates a cross-section view of a conventional interconnect structure after the step of depositing the low-k material 3 over substrate 1 and metal lines 2. An etch-back is used to etch the low-k material 3 such that the low-k dielectric material 3 only fills the gaps between metal lines 2 as shown in FIG. 1B. An SiO.sub.2 layer 4 is then deposited and planarized. Via holes 5 are etched in the SiO.sub.2 layer 4. Metal plugs 6 are formed in the via holes 5. Thereafter, a second metal layer is deposited on the SiO.sub.2 layer 4 and patterned to form metal lines 7. FIG. 1B illustrates a cross sectional view of an ideal conventional embedded low-k interconnect structure after the step of depositing and patterning the second metal layer.
In the ideal case, the low-k dielectric material 3 is isolated from the chemicals utilized to etch and clean the via holes 5 and the chemicals utilized to deposit the metal plugs 6. However, as explained above, the etch-back of the low-k material 3, which is critical for this isolation to occur, is difficult to control. Consequently, instead of the ideal case where the low-k material 3 is etched-back exactly at the top level of the metal or interconnect, the more likely case is that either the low-k material 3 is insufficiently etched-back or excessively etched-back.
FIG. 1C illustrates a cross section of a conventional interconnect structure in which the etch-back of the low-k material is insufficient (i.e., the height or level of the low-k dielectric material 3 is higher than the height of the metal lines 2). When the etch-back of the low-k material 3 is insufficient, poisoned vias 8 result. A poisoned via 8 is caused by the exposure of the low-k material 3 to the chemicals that are used in the subsequent via etch, photoresist strip and wet clean processing steps and that are not compatible with the low-k material 3. The poisoned vias 8 present a serious yield and reliability problem in the conventional embedded low-k interconnect structures. The poisoned vias 8 lead to high via or contact resistance or even via failure. Specifically, the bowl shape of poisoned vias 8 prevents the formation of a continuous seed layer or liner that is a precursor to filling the vias with plug metals. A discontinuous liner leads to poor metal growth and a poor connection.
FIG. 1D illustrates a cross section of a conventional interconnect structure in which the etch-back of the low-k material 3 is excessive (i.e., the low-k material is over-etched, exposing the sides 9 of the metal line to oxide). When the etch-back of the low-k material 3 is excessive, the capacitance between metal lines 2 (i.e., the inter-line capacitance) increases. A higher inter-line capacitance causes signals to propagate slower through the interconnect. Furthermore, the higher inter-line capacitance increases cross-talk noise, which is the unwanted transfer of signals from one metal line to another metal line.
Even if the process window is met for some metal lines, other metal lines may miss the process window. For example, the metal lines that are spaced further apart from each other experience excessive-etch-back of the low-k material (i.e., the level of the low-k material in these gaps are lower than the height of the metal lines) because the increased spacings between these metal lines. After the low-k dielectric etch-back, these spacings are only partially filled by the low-k material.
In summary, missing the process window leads to either poor interconnect integrity and reliability or degradation in performance of the circuits. Furthermore, it is very difficult or impossible to embed the low-k materials precisely in the metal gaps of different sizes by the low-k film deposition and the etch-back process. Consequently, the improvement to the overall integrated circuit performance that is provided by the incorporation of low-k material is limited.
FIGS. 2A and 2B illustrate how misalignment of vias 5a (also known as "unlanded vias") can also cause poisoned vias. Even when the process window for the etch-back of the low-k material 3a is met, the misalignment of the vias 5a with respect to the underlying metal lines 2a can also cause poisoned vias 8a. Accordingly, it is important in conventional embedded low-k interconnect structures that the vias 5a be properly aligned (also known as "landed vias") to the underlying metal lines 2a in order to isolate the low-k material 3a from the metal plugs 6a. FIGS. 2A and 2B are cross sectional views that illustrate how vias 5a can be poisoned because of misalignment even when the process window for the etch-back of the low-k material 3a is met. As noted earlier, poisoned vias 8a lead to poor plug formation that results in poor contact between the metal layers.
To address this potential misalignment problem, attempts have been made to provide some misalignment tolerance during the manufacturing process. One such approach to achieve the isolation between via plugs 6a from the low-k material 3a is to provide a larger metal area 2a at the vias 5a, thereby providing the needed misalignment tolerance.
However, increasing the metal area causes several disadvantages. First, an increased metal area causes an increased pitch, thereby reducing interconnect density per layer. Since each wafer has a predetermined number of required interconnects, a reduced interconnect density per layer forces a designer to add additional layers of interconnects to meet the required number of interconnects. Adding additional layers of interconnects increases the costs to manufacture the wafer and can also lead to lower yields.
Second, even after the metal area has been increased, special care is still required to ensure that the wafers are processed within the misalignment tolerance provided by the increased metal area. Furthermore, the precautions of increased metal area and special care in processing do not preclude the possibility of a poisoned via resulting from misalignment of the via to the metal.
Accordingly, there remains a need for an interconnect structure and fabrication method that addresses the poisoned via problem that results from misalignment and the disadvantages set forth above.